NX DESIGN SUITE
NX DESIGN SUITE is a suite of proprietary tools from NanoXplore, dedicated to the design, compilation, and programming of radiation-hardened FPGAs from the NX range. It provides a complete flow from RTL description to the final bitstream, integrating synthesis, place and route, static timing analysis, and advanced tools for debugging and IP generation. It is a comprehensive suite of tools that guarantees a controlled software chain optimized for space and all high-reliability applications.
See the documentation ↗
Detailled specifications to ensure optimal performance in every environment
- Graphical design flow: create and compile projects through an intuitive GUI.
- NXpython scripting: automate your design with a Python-based environment offering a full set of methods to create, edit, and control projects.
- NXcore IP Generator: configure and generate NanoXplore and third-party IPs directly within Impulse.
- NXscope Integration: capture and analyze signals from programmed bitstreams with a dedicated IP for HDL integration.
- Flexible Timing Constraints: define STA constraints either through NXpython scripting.


- Installation & setup guides (including License Manager Daemon configuration).
- Getting started tutorials for graphical and scripted flows.
- NXpython specifications.
- Library guides for NG-MEDIUM, NG-LARGE, and NG-ULTRA.
- NXscope quick start & detailed manuals.
- Design constraint references (NXDC).
- Application Notes describing the test infrastructure.
- A detailed User Manual for navigating the environment.
- ReadMe documentation covering advanced features such as argparser-based test case launching.

Guiding your project from concept to long term success.
For a complete library of user guides, reference manuals and technical documentation, or if you have any questions about our products, head to our Wiki Page.
See the documentation ↗Download the complete overview.
Explore the NX Design Suite product brief, including its unified design flow, integrated tools and key features for streamlined FPGA development.
Download PDF ↗